Recently, following the tendency of electronic devices toward becoming smaller and lighter, a mounting substrate which is a part of these devices is required to perform higher mounting density. The mounting technique itself has become one of the major elements in the field of development of new electronic devices. This mounting technique can be divided into two components: 1. surface mounting components such as semiconductors or chip components, and 2. substrates for mounting and connecting these components electrically including its mounting method. It is widely known that semiconductors have increasingly more chip sizes and terminals for attaining higher integration density and functional improvements. Therefore, the terminal pitch is tending toward becoming narrower For example, terminal pitch is 0.3 mm at present, whereas the pitch was 0.5 mm in the past. If the pitch were narrower than 0.3 mm, it would be difficult to apply a conventional solder method for mounting. The chip on board (COB) technique, which mounts semiconductors directly on substrates, will be considered more important in the future than the well-known "package". Therefore, the COB technique has been researched in various fields. Furthermore, the tendency toward smaller chip components has developed so far that nowadays 1005 chip (1.0.times.0.5 mm) is used daily. Similar to the case with semiconductors, it would be difficult to produce smaller chip components than this size since the mounting method causes a limit on size reduction. In addition, mounting costs would be significantly higher.
On the other hand, the dominant current in electronic devices is moving toward digitalized circuits which are accompanied by higher frequency and acceleration. As a result, mounting substrates can no longer sidestep the noise and heat problems. In order to cope with this problem of higher frequency and acceleration, a usual method which is practiced at present is to manufacture a prototype first, and then to modify it again, if any problem should occur. Therefore, a great amount of time has been spent for the development of electronic devices, and this method prolongs the development period. It is desired in the future that the development of substrates is conducted in such a way that a simulation of heat, transmission lines, and noise takes place at the planning stage, and that the results of that simulation are fed back to the substrate planning so that one prototype is enough for completing the process. However, this substrate planning system is still a long way from perfect operation. Thus, a designing method in which know-how from past experience is used is still considered to be in the main stream at the moment. In any case, counter-methods to combat the current toward higher frequency are surely to be based on substrates and mounting forms which have shorter wirings.
As described above, the surface mounting components as well as the substrate techniques are important aspects for attaining electronic devices with high mounting density in the future. At present, one high-density mounting substrate used generally is a glass-epoxy substrate. This substrate is made of glass woven fabrics which are impregnated with epoxy resin to form an insulating substrate material. Glass-epoxy multilayer substrates had been developed for use with computers in the past, but nowadays they are widely applied for consumer use. A method of manufacturing a glass-epoxy multilayer substrate comprises the steps of:
(1) adhering a Cu foil by heat-pressing the above-mentioned material which was made of glass woven fabrics impregnated with epoxy (this is called a prepreg);
(2) patterning the Cu foil by a photolithographic technique to form wiring for an internal layer;
(3) forming a multilayer laminate by further heat-pressing with the use of another prepreg and a Cu foil;
(4) drilling through-holes into the laminate and forming a Cu electrode on the inner wall of the through-holes by an electrolytic plating method, thereby connecting the layers electrically; and
(5) etching the Cu surface into patterns.
FIG. 6 is a schematic view of this glass-epoxy multilayer substrate. Referring to FIG. 6, reference numeral 500 denotes an insulating base material made of glass woven fabrics impregnated with epoxy resin; 501, Cu wirings in internal layers; 502, drilled holes made after being formed into a laminated multilayer; 503, a Cu layer on inner walls formed by a plating method; and 504, circuit patterns on the upper most layer. This drill process and the Cu-plated through-holes were established through the development of techniques in which this kind of glass-epoxy base material is used to connect internal layers to outside layers electrically. This method is also widely acknowledged in the world.
However, in view of the demand for higher density in the future as mentioned above, this method can not be considered satisfactory. The reason is that a usual glass-epoxy multilayer substrate is disposed with through-holes which consequently reduce the wiring space. And thus, when high-density wirings are performed, the necessary wirings must take a round about way thereby lengthening the wirings. In addition, it is difficult to conduct an automatic wiring by CAD (computer aided design) because there is not enough space for wiring. Furthermore, following the present tendency of forming smaller holes, the drill processing can not be applied so easily. In fact, this tendency raises the cost ratio of the drill processing within the entire costs. Not only that, the Cu-plating process which is necessary for through-holes is problematic from an environmental point of view.
In order to solve the above-mentioned problems, a number of new multilayer substrates have been developed in the field of multilayer substrates. First, as a technique which applies the method of forming substrates with Cu-plated through-holes by a drill is to form SVH (Semi-Buried Via Hole) multilayer substrates. This method of forming SVH substrates is conducted by means of via connection consisting of not only through-holes, but also via connections on the surface which enables more high-density wirings than with the through-hole-type substrate. Via parts on the surface are filled with insulating resin which are then Cu-plated thereon in order to form mounting pads for components on top of the via parts. According to this method, through-holes for insert components are only present on the surface, and therefore, components can be mounted with high-density. But this method is an improved technique of forming the above-mentioned glass-epoxy multilayer so that it still suffers from the same problem with the difficulty in drill processing and the necessity for Cu-plating.
On the other hand, new multilayer substrates having a perfect inner-via-hole (IVH: Interstitional Via Hole) structure are disclosed, for example, in a SLC (Surface Laminated Circuit, registered trademark of IBM) substrate and a multilayer substrate using thermoplastic resin. A method of manufacturing SLC substrates comprises the steps of providing a double sided substrate having usual Cu-patterned layers, coating the surface of this substrate with resin as an insulating material, forming via holes by a photolithographic method, adding Cu-plating on the entire surface, and connecting a bottom conductor, a via hole part, and wiring on a surface layer. Then, by applying the same photolithographic method, patterns are formed. This process is repeated to form a multilayer. At present, this method is especially watched with keen interest because it can form highly accurate wirings at an extremely low cost. The problems with this method is that the adhesion strength between the insulating material and the Cu-electrode is low, and substrates can warp easily due to the difference in thermal expansion between the core substrate and the resin.
A multilayer substrate using thermoplastic resin is manufactured by first disposing holes in a thermoplastic sheet-type base material, and printing patterns on the surface of the sheet with conductive resin paste made of silver, and then, by heat-pressing another sheet formed separately on top to form a multilayer substrate. The problem in this case is that the thermoplastic resin does not have heat resistance. In addition, the conductive resin paste has high wiring resistance, and it is also difficult to solder the surface part. Nevertheless, both methods are attracting attention since they have the big advantage of forming multilayer substrates having a perfect inner-via-hole (IVH) structure.
Another technique is disclosed in Laid-open Japanese patent application No. (Tokkai Sho) 50-94495 and in U.S. Pat. No. 3,620,873 in which an electrical connector (rubber connector) was used to connect NESA glass made of liquid-crystal elements and a flexible printed substrate (FPC). This connector is in the form of laminated layers which are piled up such that layers of silicon rubber mixed with carbon black and layers without carbon black are present as alternating layers.
However, the above-mentioned conventional methods have the following problems. First, the conventional structure does not allow the processing of through-holes easily once the substrate is laminated into a multilayer substrate. This constitution presents difficulties for coping with the tendency toward high-density wiring. Namely, it is necessary to process even smaller holes, and it is also difficult to process holes to match the wirings in the internal layers. As for the processing of more minute holes, the diameter of the drill is required to be smaller and smaller, and the costs for processing this kind of drill become significant. It is also anticipated that accurate holes can not be formed in the thickness direction with minute drills. Furthermore, although the accuracy in positioning wirings in an internal layer against wirings on external layers needs to be higher and higher, it is becoming even more and more difficult to process holes at exact places due to a size gap or elongation of substrate materials. It is still a big problem to position internal layers to each other exactly in the present current toward higher build-up layers.
As a result of the problems mentioned above, the conventional substrates used for circuits have a limit in the number of through-hole connections which can be performed per unit area and also in the density of circuit patterns. Therefore, the conventional method presents major difficulties for obtaining multilayer substrates used for high-density mounting which will be more and more in demand.
Furthermore, the rubber connector disclosed in the above-mentioned Laid-open Japanese patent application No. (Tokkai Sho) 50-94495 and in U.S. Pat. No. 3,620,873 had the problem of having high electrical resistance of several k.OMEGA./mm.sup.2 because carbon black is mixed in the silicone rubber.